1. Field of the Invention
The present invention relates to a digital processing system and, particularly, to a method and apparatus for bit operational process suitably used in an image processing system having a bit-map display.
2. Background
The conventional system will first be described by using an example of image processing shown in FIG. 1. In the figure, reference symbol M1 denotes a memory area storing image data in 1-to-1 correspondence to a CRT (Cathode Ray Tube) screen, M2 denotes a memory area storing image data to be added to the image data in M1, XA and XB denote partial areas in M1 and M2, respectively, for which image data processing takes place, WA0, WA1, WA2, WB0 and WB1 denote boundaries of data words having a word length of 16 bits, for example, R0 through Rm represent raster lines for the partial areas XA and XB, na and nb represent displacements of the leading edges of the areas XA and XB from the word boundaries WA0 and WB0, respectively, A0 through An and B0 through Bn represent addresses of word data in the areas XA and XB , and MFY denotes a modification unit implementing the alignment and processing for the areas XA and XB having different starting bit positions na and nb.
Since the currently available processing unit such as a microprocessor deals with data and makes access to the memory in units of a word or a byte, the memory areas M1 and M2 shown in FIG. 1 have a word or byte structure. However, in image processing, a partial screen area to be processed is specified the outside of the system without regard to the word boundary as shown by areas XA and XB in FIG. 1. On this account, image processing for combining the partial areas XA and WB needs a modification unit MFY with the following three processing functions.
(1) Rearrangement of word data so that processing can take place on a word-wide basis between data for areas XA and XB with different starting bit positions na and nb.
(2) Separation of data section from word-wide data e.g., na bits, in each of addresses A0, A3, . . . , Anxe2x88x922 so that it is retained unchanged in the processing.
(3) Data processing in any specific number of bits (bit width) so that monochrome display is implemented using one bit per pixel while color display uses a plurality of bits per pixel (generally four bits per pixel).
The operation of the modification unit having these functions will be described in connection with FIG. 2. Throughout the following description, it is assumed that the image data memory is addressed in units of a word.
FIG. 2 shows a 2-word register SRC(A) and SRC(B) for storing data read out of the processing area XB, a 2-word register DST(A) and DST(B) for storing data read out of the processing area XA, and a 2-word register DST(A) and DST(B) for storing the result of processing for the contents of the registers SRC(A, B) and DST(A, B). The modification unit MFY performs rotation of the register SRC(A, B), i.e., shift of SRC content with bit 0 of SRC (A) linked with bit F of SRC(B), depending on the values of SN (i.e., nb) and DN (i.e., na) representing the starting bit positions of the processing areas XA and XB, as follows.
(a) For SN greater than DN: Rotate the SRC content left by a number of bits of SN-DN.
(b) For SN less than DN: Rotate the SRC content right by a number of bits of DN-SN.
(c) For SN=DN: No operation.
In this way, bit addresses nb(SN) and na(DN) are used to align the operation starting bit position.
Consequently, the starting bit position of the SRC content is adjusted to that of the DST content. The bit width of processing, WN, is set in advance, and the remaining portion of data is left unchanged. Although in FIG. 2 the result register MRG(A, B) is provided independently of DST(A, B), they may be arranged in common. After the subsequent processing, the original bit position of the SRC content is restored automatically.
Next, the 4-bit image processing for the areas XA and XB by the modification unit MFY will be described in connection with FIGS. 3, 4, 5 and 6. The process shown in FIG. 3 includes step S1 of setting the starting address A0 for the processing area XA, step S2 of setting DN to the starting bit position (address) na, step S3 of setting the starting address B0 for the processing area XB, step S4 of setting SN to the starting bit position (address) nb, step S5 of the process implemented by the modification unit MFY mentioned above, steps S6-S9 for the area XB for obtaining the next bit address (S6), setting the next SN (S7), incrementing the address in word units (S8) and reading next word data (S9), and steps S10-S14 for the area XB for obtaining the next bit address (S10), setting the next DN (S11), writing the result of process in the register MRG(A) (S12), incrementing the address in word units (S13) and reading the next word data (S14). The process further includes decision steps SB1 and SB2, which implement the following operations.
(I) Decision step SB1
This step tests as to whether the next SN address of SRC resulting from the steps S6 and S7 as in the following expression (1) reaches beyond the word boundary as in the following expression (2), and controls the sequence to fetch the next word data when the condition (2) is met.
SN=SN+WNxe2x80x83xe2x80x83(1)
SNxe2x89xa7(10)HEXxe2x80x83xe2x80x83(2)
(II) Decision step SB2
This step tests as to whether the next DN address of DST resulting from the steps S10 and S11 reaches beyond the word boundary as in the following expression (3), and controls the sequence to write data in the register MRG(A) to the area XA when the condition (3) is met, which indicates the end of operation at the current word boundary.
DNxe2x89xa7(10)HEXxe2x80x83xe2x80x83(3)
The above operations for one raster (R0) will be described in more detail in connection with FIGS. 4, 5, and 6.
FIG. 4 is the case of condition,       DN    +    WN    =                              (          A          )                HEX            +                        (          4          )                HEX               less than                   (        10        )            HEX      
Then, reading of the next word data and writing of process result do not take place.
FIG. 5 is the case of condition,       DN    +    WN    =                              (          E          )                HEX            +                        (          4          )                HEX               greater than                   (        10        )            HEX      
Then, reading of the next word data and writing of process result take place.
FIG. 6 is the case of condition,       SN    +    WN    =                              (          D          )                HEX            +                        (          4          )                HEX               greater than                   (        10        )            HEX                  and      ⁢              xe2x80x83            ⁢      DN        +    WN    =                              (          2          )                HEX            +                        (          4          )                HEX               less than                   (        10        )            HEX      
Then, reading of the next SRC word data takes place, but writing of the process result does not take place.
The foregoing prior art processing system involves the following drawbacks.
(1) The conventional microprocessor of word addressing type needs register rotation and word boundary check by software in implementing bit block operations, resulting in a complex system control.
(2) Fetching of data from the processing areas XA and XB needs different access timing depending on the current bit position with respect to the word boundary, resulting in a complex software control.
(3) The amount of data stored in the memory areas M1 and M2 will range as much as from 100 kilo-bytes to several mega-bytes, and the process shown in FIG. 3 with the bit width WN being set as large as one byte (8 bits) will take a total number of steps of the order of 106, and therefore the number of processing steps needs to be reduced drastically.
Furthermore, the conventional microprocessor merely allows bit operations such as arithmetic shift, logical shift, bit set, bit reset, etc., but as to other arithmetic and logic operations, etc., it is impossible to carry out the operations except only in a fixed bit length such as a byte or word. On this account, in order to achieve xe2x80x9craster operationxe2x80x9d on a bit-map display having a memory in correspondence at each point of on/off control to the display screen for implementing an image process between separate rectangular areas of arbitrary size on the screen, the above-mentioned bit operations do not suffice the purpose, but operations of data with any bit width at any position in each word becomes necessary. If such operations are intended to be performed using a microprocessor, input data is shifted for bit alignment, an operation is conducted on the data, the resultant data is shifted for alignment with another data to be merged, and after the merging operation the resultant data is stored in the original memory location. These sequential operations take too long a time, and fast image processing cannot be expected.
There is a method of solving this problem, in which there is added to the system a barrel shifter that is capable of multi-bit shift at the same operating speed as the single-bit shift, and a merging circuit. However, despite the capability of bit alignment by the barrel shifter, the processor is limited to fixed word-length operations and external memory access usually in 8-bit or 16-bit length, and the restricted hardware ability for implementing arbitrary bit width operations need to be covered by complex software processes through the use of simple bit operations. An example of the processor for implementing the foregoing operations is Micro Processor, model Am 29116, manufactured by ADVANCED MICRO DEVICES.
It is an object of this invention to provide a method and apparatus for bit operation with the intention to simplify and speed up the computation between data with arbitrary number of bits at arbitrary position in each data word.
Another object of this invention is to provide a bit processing system capable of easily accessing an external data memory under word address control for the internal processing under bit address control.
Still another object of this invention is to provide a bit operation unit capable of easily executing an arithmetic and logic operation for bits with any number of bits at any position in each data word.
A further object of this invention is to provide a bit operation processing system capable of bit and word address control and external memory access control on a hardware basis so that the overhead software processing is reduced to enhance the system performance.
In order to achieve the above objectives, this invention has features as follows.
(1) Internal computations are controlled entirely on the basis of bit addressing.
(2) A bit address operation unit is provided for bit addressing control in addition to the word address operation unit for word addressing control.
(3) The bit address operation unit operates to add the current operation starting bit address to the bit width of bits to be operated.
(4) The bit address and word address operation units have an interface through the carry signal produced by the bit address operation unit.
(5) The carry signal of the bit address operation unit, when seen from the internal processing control, is an anticipation signal indicating that the current starting bit position will reach beyond the word boundary in the next operation cycle. Accordingly, the carry signal is used to trigger the external memory access for fetching word data necessary for the bit operation at the word boundary.
(6) The bit address and word address operation units, share the hardware components, but have the distinct logical functions relating through the carry signal.
(7) The bit address operation unit operates cyclically in a word period, and its output represents the relative bit address counted from each word boundary.
(8) The carry signal produced at a certain bit position of the bit address operation unit creates the boundary of words of 2n bits.
(9) The bit address operation unit performs addition of a operation bit width for each register independently, allowing bit operations of arbitrary number of bits.
On the other hand, in order for the bit-map display to achieve operation between data of rectangular screen areas, i.e., raster operation, it is necessary to achieve operation between data with any bit width at any position in the data word. For the computation of data with any bit width by a fixed bit-width processor, the absent bit oppositions of input data need to be filled. In simple arithmetic operations, a fixed bit width processor can deal with data with reduced number of bits by filling 0""s bits in the lower absent bit positions to obtain a correct result including the carry bit. In the carry adding operation, lower absent bit positions must be filled with 1""s bits to obtain a correct result. Logical operations between data are implemented for each corresponding bit separately, and the number of significant bits is arbitrary for the processor to obtain a correct result, except for the flags, which values are correct when absent bit positions are filled with 0""s or 1""s bits selectively. Accordingly, in carrying out an arithmetic or logic operation for data with arbitrary number of bits, input data are placed at high order bit positions of the processor, with absent bit positions being filled with 0""s bits or 1""s bits depending on the type of operation, thereby to obtain a completely correct result.